MOTOROLASEMICONDUCTOR TECHNICAL DATAMC14094B8-Stage Shift/Store Registerwith Three-State OutputsThe MC14094B combines an 8–stage shift register with a data latch foreach stage and a three–state output from each latch.Data is shifted on the positive clock transition and is shifted from theseventh stage to two serial outputs. The QS output data is for use inhigh–speed cascaded systems. The Q′S output data is shifted on thefollowing negative clock transition for use in low–speed cascaded systems.Data from each stage of the shift register is latched on the negativetransition of the strobe input. Data propagates through the latch while strobeis high.Outputs of the eight data latches are controlled by three–state bufferswhich are placed in the high–impedance state by a logic Low on OutputEnable.•Three–State Outputs•Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature Range•Input Diode Protection•Data Latch•Dual Outputs for Data Out on Both Positive and Negative ClockTransitions•Useful for Serial–to–Parallel Data Conversion•Pin–for–Pin Compatible with CD4094BL SUFFIXCERAMICCASE 620P SUFFIXPLASTICCASE 648D SUFFIXSOICCASE 751BORDERING INFORMATIONMC14XXXBCPMC14XXXBCLMC14XXXBDPlasticCeramicSOICTA = – 55° to 125°C for all packages.PIN ASSIGNMENTSTROBE12345678161514131211109VDDOUTPUTENABLEQ5Q6Q7Q8Q′SQSMAXIMUM RATINGS* (Voltages Referenced to VSS)SymbolVDDVin, VoutIin, IoutPDTLParameterDC Supply VoltageInput or Output Voltage (DC or Transient)Input or Output Current (DC or Transient),per PinPower Dissipation, per Package†Storage TemperatureValue– 0.5 to + 18.0– 0.5 to VDD + 0.5± 10500260UnitVVmAmW_C_CDATACLOCKQ1Q2Q3Q4VSSTstg– 65 to + 150Lead Temperature (8–Second Soldering)*Maximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_CCeramic “L” Packages: – 12 mW/_C From 100_C To 125_COutputEnable001111Parallel OutputsStrobeXX0111DataXXX011Q1ZZNo Chg.01No Chg.QNZZNo Chg.QN–1QN–1No Chg.Serial OutputsQS*Q7No Chg.Q7Q7Q7No Chg.Q′SNo Chg.Q7No Chg.No Chg.No Chg.Q7ClockThis device contains protection circuitry toguard against damage due to high staticvoltages or electric fields. However, pre-cautions must be taken to avoid applications ofany voltage higher than maximum rated volt-ages to this high–impedance circuit. For properoperation, Vin and Vout should be constrainedto the range VSS v (Vin or Vout) v VDD.Unused inputs must always be tied to anappropriate logic voltage level (e.g., either VSSor VDD). Unused outputs must be left open.Z = High ImpedanceX = Don’t Care*At the positive clock edge, information in the 7th shift register stage is transferred toQ8 and QS.REV 31/94©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995MC14094B1ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)CharacteristicSymbolVOLVDDVdc5.010155.010155.010155.010155.05.010155.0101515—5.010155.01015Min———– 55_C25_C125_CMaxMin———Typ #000MaxMin———MaxUnitVdcOutput VoltageVin = VDD or 0 “0” Level0.050.050.05———0.050.050.05———0.050.050.05———“1” LevelVin = 0 or VDDVOH4.959.9514.95———4.959.9514.95———5.010154.959.9514.95———VdcInput Voltage“0” Level(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)“1” Level(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)VILVdc1.53.04.0——————————2.254.506.752.755.508.251.53.04.0——————————1.53.04.0——————————VIHVdc3.57.0113.57.0113.57.011Output Drive Current(VOH = 2.5 Vdc) (VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)(VOL = 0.4 Vdc) (VOL = 0.5 Vdc)(VOL = 1.5 Vdc)SourceIOHmAdc– 3.0– 0.64– 1.6– 4.20.641.64.2—————– 2.4– 0.51– 1.3– 3.40.511.33.4—————– 4.2– 0.88– 2.25– 8.80.882.258.8– 1.7– 0.36– 0.9– 2.40.360.92.4—————SinkIOLmAdcInput CurrentInput Capacitance(Vin = 0)Iin± 0.1—5.01020±0.000015.00.0050.0100.015± 0.17.55.01020± 1.0—150300600µAdcpFµAdcCinQuiescent Current(Per Package)IDDTotal Supply Current**†(Dynamic plus Quiescent,Per Package)(CL = 50 pF on all outputs, allbuffers switching)3–State Output Leakage CurrentITIT = (4.1 µA/kHz) f + IDDIT = (14 µA/kHz) f + IDDIT = (140 µA/kHz) f + IDDµAdcITL15—± 0.1—± 0.0001± 0.1—± 3.0µA#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.**The formulas given are for the typical characteristics only at 25_C.†To calculate total supply current at loads other than 50 pF:IT(CL) = IT(50 pF) + (CL – 50) Vfkwhere: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.MC14094B2MOTOROLA CMOS LOGIC DATASWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)CharacteristicOutput Rise and Fall TimetTLH, tTHL = (1.35 ns/pF) CL + 33 nstTLH, tTHL = (0.6 ns/pF) CL + 20 nstTLH, tTHL = (0.4 ns/pF) CL + 20 nsPropagation Delay TimeClock to Serial out QStPLH, tPHL = (0.90 ns/pF) CL + 305 nstPLH, tPHL = (0.36 ns/pF) CL + 107 nstPLH, tPHL = (0.26 ns/pF) C L + 82 nsClock to Serial out Q’StPLH, tPHL = (0.90 ns/pF) CL + 350 nstPLH, tPHL = (0.36 ns/pF) CL + 149 nstPLH, tPHL = (0.26 ns/pF) CL + 62 nsClock to Parallel outtPLH, tPHL = (0.90 ns/pF) CL + 375 nstPLH, tPHL = (0.35 ns/pF) CL + 177 nstPLH, tPHL = (0.26 ns/pF) CL + 122 nsSymboltTLH,tTHLVDDVdc5.01015Min———Typ #1005040Max20010080UnitnstPLH,tPHLns5.010155.010155.010155.010155.010155.010155.010155.010155.0101551015——————————————————350125952301107542019513529014510014075552259570603020600250190460220150840390270580290200280150110450190140—————————Strobe to Parallel outtPLH, tPHL = (0.90 ns/pF) CL + 245 nstPLH, tPHL = (0.36 ns/pF) C L + 127 nstPLH, tPHL = (0.26 ns/pF) CL + 87 nsOutput Enable to OutputtPHZ, tPZL = (0.90 ns/pF) CL + 95 nstPHZ, tPZL = (0.36 ns/PF) CL + 57 nstPHZ, tPZL = (0.26 ns/pF) CL + 42 nstPLZ, tPZH = (0.90 ns/pF) CL + 180 nstPLZ, tPZH = (0.36 ns/pF) CL + 77 nstPLZ, tPZH = (0.26 ns/pF) CL + 57 nstPHZ,tPZLtPLZ,tPZHtsuSetup TimeData in to ClockHold TimeClock to Data125553502020nsth– 40– 1001005040———nsClock Pulse Width, HightWH20010083——————nsClock Rise and Fall Timetr(cl)tf(cl)fcl155.04.0µsClock Pulse Frequency5.010155.010152.55.06.01.252.53.0———MHzStrobe Pulse WidthtWL20080701004035ns*The formulas given are for the typical characteristics only at 25_C.#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.3–STATE TEST CIRCUITFOR tPHZ AND tPZHVSSFOR tPLZ AND tPZLVDDO.E.DATASTCLOCK1 kOUTPUT50 pFMOTOROLA CMOS LOGIC DATAMC14094B3BLOCK DIAGRAMREGISTER STAGE 1CLOCK2CLOCKLATCH 1STROBE3–STATE BUFFER 1VDD*SERIALDATA INCLOCKCLOCKSTROBESTROBE4Q1CLOCK15CLOCKSTROBE*2OUTPUTENABLE34567REGISTER STAGE 2REGISTER STAGE 3REGISTER STAGE 4REGISTER STAGE 5REGISTER STAGE 6REGISTER STAGE 7LATCH 2LATCH 3LATCH 4LATCH 5LATCH 6LATCH 73–STATE BUFFER23–STATE BUFFER33–STATE BUFFER43–STATE BUFFER53–STATE BUFFER63–STATE BUFFER7567141312Q2Q3Q4Q5Q6Q78REGISTER STAGE 8CLOCKCLOCKLATCH 8STROBESTROBECLOCK3–STATE BUFFER811Q8103Q′S*CLOCKCLOCKCLOCKCLOCK*Input Protection DiodesCLOCK1*STROBESTROBESTROBECLOCK9QSDYNAMIC TIMING DIAGRAMtWHCLOCKtsu2tr50%50%90%10%tf3thDATA INtWL1STROBE15OUTPUTENABLEtPLH90%10%tTLHtTHLtPHL90%10%tPLH50%tPLH50%tPHZ90%10%tPHL50%tPLHtPZHtPLZ50%tPZL90%10%NQ1 ³ Q79QStPHL50%10Q′S50%MC14094B4MOTOROLA CMOS LOGIC DATAOUTLINE DIMENSIONSL SUFFIXCERAMIC DIP PACKAGECASE 620–10ISSUE V–A–169NOTES:1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4.DIMENSION F MAY NARROW TO 0.76 (0.030)WHERE THE LEAD ENTERS THE CERAMICBODY.DIMABCDEFGHKLMNINCHESMINMAX0.7500.7850.2400.295–––0.2000.0150.0200.050 BSC0.0550.0650.100 BSC0.0080.0150.1250.1700.300 BSC0 _15 _0.0200.040MILLIMETERSMINMAX19.0519.936.107.49–––5.080.390.501.27 BSC1.401.652.54 BSC0.210.383.184.317.62 BSC0 _15 _0.511.01–B–18CL–T–SEATINGPLANENEFDG16 PLKMJ16 PL0.25 (0.010)MMTBS0.25 (0.010)TASP SUFFIXPLASTIC DIP PACKAGECASE 648–08ISSUE R–A–169NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.DIMABCDFGHJKLMSINCHESMINMAX0.7400.7700.2500.2700.1450.1750.0150.0210.0400.700.100 BSC0.050 BSC0.0080.0150.1100.1300.2950.3050 _10 _0.0200.040MILLIMETERSMINMAX18.8019.556.356.853.694.440.390.531.021.772.54 BSC1.27 BSC0.210.382.803.307.507.740 _10 _0.511.01B18FSCL–T–HKGD16 PLSEATINGPLANEJTAMM0.25 (0.010)MMOTOROLA CMOS LOGIC DATAMC14094B5OUTLINE DIMENSIONSD SUFFIXPLASTIC SOIC PACKAGECASE 751B–05ISSUE J–A–NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERSMINMAX9.8010.003.804.001.351.750.350.490.401.251.27 BSC0.190.250.100.250 7 __5.806.200.250.50INCHESMINMAX0.3860.3930.1500.1570.0540.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090 7 __0.2290.2440.0100.019169–B–18P8 PL0.25 (0.010)MBSGFKC–T–SEATINGPLANERX 45_MD16 PLMJ0.25 (0.010)TBSASDIMABCDFGJKMPRHow to reach us:
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MC14094B6
MOTOROLA CMOS LOGIC DATA