MC100EP140
3.3VĄECL Phase-FrequencyDetector
The MC100EP140 is a three state phase frequency–detector intended forphase–locked loop applications which require a minimum amount of phaseand frequency difference at lock. Since the part is designed with fullydifferential internal gates, the noise is reduced throughout the circuit,especially at high speeds. The basic operation of a Phase/FrequencyDetector (PFD) is to “compare” an incoming signal (feedback) to a setreference signal. When the Reference (R) and Feedback (FB) inputs areunequal in frequency and/or phase, the differential UP (U) and DOWN(D) outputs will provide pulse streams which, when subtracted andintegrated, provide an error voltage for control of a VCO. Detectorstates of operation are shown in the Figure 2 and the State Table.The device is packaged in a small outline, surface mount 8–leadSOIC package. The typical output amplitude of the EP140 is 400 mV,allowing faster switching time and greater bandwidth. For properoperation, the input edge rate of the R and FB inputs should be lessthan 5 ns.
More information on Phase Lock Loop operation and application canbe found in AND8040.
The pinout is shown in Figure 1, the logic diagram in Figure 3, andthe typical termination in Figure 5.
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MARKINGDIAGRAM
8
81
SO–8D SUFFIXCASE 751
1
KP= MC100EP
A= Assembly LocationL= Wafer LotY= Year
W= Work Week
KP140ALYW
•••••
500 ps Typical Propagation DelayMaximum Frequency > 2.1 GHz TypicalFully Differential Internally
Advanced High Band Output Swing of 400 mVTransfer Gain:1.0 mV/Degree at 1.4 GHz
1.2 mV/Degree at 1.0 GHz
Rise and Fall Time: 100 ps Typical
ORDERING INFORMATION
Device
MC100EP140DMC100EP140DR2
PackageSO–8SO–8
Shipping98 Units/Rail2500 Units/Reel
•
•The 100 Series Contains Temperature Compensation•PECL Mode Operating Range: VCC = 3.0 V to 3.6 V ••
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –3.6 VOpen Input Default State
© Semiconductor Components Industries, LLC, 20021
September, 2002 – Rev. 5
Publication Order Number:
MC100EP140/D
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MC100EP140
VCC8
R7
FB6
VEE5
PIN DESCRIPTION
PIND, DU, UR*FB*VCCFUNCTIONDifferential Down OutputsDifferential Up OutputsECL Reference InputECL Feedback InputPositive SupplyNegative Supply1U2U
3D4D
VEE*Pins will default LOW when left open.
Figure 1. 8–Lead Pinout (Top View)
STATE TABLE
RRPHASE DETECTORSTATEPUMP DOWN
2–1–2
2
2–11–22
FBFBPUMP UP2–3–2
2
LHHL
LLHL
LHLL
LLLL
2–33–22
INPUTR
FB
OUTPUTU
D
FB1U = LD = HPumpDown2U = LD = LPump Up3U = HD = LRLLHL
LHLL
LLLL
LHLL
Figure 2. Phase Detector Logic Model
UR
AASResetVEEBResetFB
DRBSDFFDRUFFCDCACAUUResetResetBDDDBFigure 3. Logic Diagram
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MC100EP140
ATTRIBUTESCharacteristicsInternal Input Pulldown ResistorInternal Input Pullup ResistorESD ProtectionHuman Body ModelMachine ModelCharged Device ModelValue75 kW37.5 kW> 2 kV> 200 V> 2 kVLevel 1UL–94 V–0 @ 0.125 in457 DevicesMoisture Sensitivity, Indefinite Time Out of Drypack (Note 1)Flammability RatingTransistor CountMeets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test1.For additional information, see Application Note AND8003/D.Oxygen Index: 28 to 34MAXIMUM RATINGS (Note 2)
SymbolVCCVEEVIIoutTATstgθJAθJCTsolParameterPECL Mode Power SupplyNECL Mode Power SupplyPECL Mode Inut VoltagePECL Mode Input VoltageNECL Mode Input VoltageOutput CurrentOperating Temperature RangeStorage Temperature RangeThermal Resistance (Junction–to–Ambient)Thermal Resistance (Junction–to–Case)Wave Solder0 LFPM500 LFPMstd bd<2 to 3 sec @ 248°C8 SOIC8 SOIC8 SOICCondition 1VEE = 0 VVCC = 0 VVEE = 0 VVCC = 0 VContinuousSurgeVI VCCVI VEECondition 2Rating6–66–650100–40 to +85–65 to +15019013041 to 44265UnitsVVVVmAmA°C°C°C/W°C/W°C/W°C2.Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)–40°CSymbolIEEVOHVOLVIHVILIIHIILCharacteristicPower Supply CurrentOutput HIGH Voltage (Note 4)Output LOW Voltage (Note 4)Input HIGH Voltage (Single–Ended)Input LOW Voltage (Single–Ended)Input HIGH CurrentInput LOW Current0.5Min552155175520751355Typ7022801880Max8524052005242016751500.5Min60215517552075135525°CTyp7422801880Max9024052005242016751500.5Min63215517552075135585°CTyp7822801880Max932405200524201675150UnitmAmVmVmVmVµAµANOTE:EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Thecircuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –0.3 V.4.All loading with 50 W to VCC–2.0 volts.
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MC100EP140
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –3.6 V to –3.0 V (Note 5)–40°CSymbolIEEVOHVOLVIHVILIIHIILCharacteristicPower Supply CurrentOutput HIGH Voltage (Note 6)Output LOW Voltage (Note 6)Input HIGH Voltage (Single–Ended)Input LOW Voltage (Single–Ended)Input HIGH CurrentInput LOW Current0.5Min55–1145–1545–1225–1945Typ70–1020–1420Max85–895–1295–880–16251500.5Min60–1145–1545–1225–194525°CTyp74–1020–1420Max90–895–1295–880–16251500.5Min63–1145–1545–1225–194585°CTyp78–1020–1420Max93–895–1295–880–1625150UnitmAmVmVmVmVµAµANOTE:EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Thecircuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5.Input and output parameters vary 1:1 with VCC.6.All loading with 50 W to VCC–2.0 volts.
AC CHARACTERISTICS VCC = 0 V; VEE = –3.0 V to –3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 7)
–40°CSymbolfmaxtPLH,tPHLtJITTERVPPtrtfCharacteristicMaximum Frequency(See Figure 4 Fmax/JITTER)Propagation Delay to Output DifferentialCycle–to–Cycle Jitter(See Figure 4 Fmax/JITTER)Input Voltage SwingOutput Rise/Fall Times (20% – 80%)Q, Q40050R to U, FB to DFB to U, R to D300400MinTyp> 2450600.2800906002800< 1120018040060325450MaxMin25°CTyp> 2475650.2800100625850< 1120020040070350500MaxMin85°CTyp> 2500700.2800120650900< 11200220MaxUnitGHzpspsmVps7.Measured using a 750 mV VPP pk–pk, 50% duty cycle, clock source. All loading with 50 W to VCC–2.0 V.
600500VOUTpp (mV)400300200
(JITTER)100
643210
04008001200160020002400
FREQUENCY (MHz)
Figure 4. Fmax/Jitter
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JITTEROUT ps (RMS)5元器件交易网www.cecb2b.com
MC100EP140
QDriverDeviceQ50W50WDReceiverDeviceDVTT
VTT=VCC– 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404AN1405AN1406AN1504AN1568AN1650AN1672AND8001AND8002AND8009AND8020AND8040
––––––––––––
ECLinPS Circuit Performance at Non–Standard VIH LevelsECL Clock Distribution TechniquesDesigning with PECL (ECL at +5.0 V)Metastability and the ECLinPS FamilyInterfacing Between LVDS and ECLUsing Wire–OR Ties in ECLinPS DesignsThe ECL Translator GuideOdd Number Counters DesignMarking and Date Codes
ECLinPS Plus Spice I/O Model KitTermination of ECL Logic DevicesPhase Lock Loop Operation
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC100EP140
PACKAGE DIMENSIONS
SO–8D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–07ISSUE AA
–X–A85NOTES:
1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDE MOLDPROTRUSION.
4.MAXIMUM MOLD PROTRUSION 0.15 (0.006) PERSIDE.
5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL INEXCESS OF THE D DIMENSION AT MAXIMUMMATERIAL CONDITION.
6.751-01 THRU 751-06 ARE OBSOLETE. NEWSTANDAARD IS 751-07
MILLIMETERSMINMAX4.805.003.804.001.351.750.330.511.27 BSC0.100.250.190.250.401.270 _8 _0.250.505.806.20INCHESMINMAX0.1890.1970.1500.1570.0530.0690.0130.0200.050 BSC0.0040.0100.0070.0100.0160.0500 _8 _0.0100.0200.2280.244B1S40.25 (0.010)MYM–Y–GKC–Z–HD0.25 (0.010)
MSEATINGPLANENX 45_0.10 (0.004)MJZY
SX
SDIMABCDGHJKMNShttp://onsemi.com
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MC100EP140
Noteshttp://onsemi.com
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MC100EP140
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to makechanges without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for anyparticular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and allliability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or deathmay occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLCand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatSCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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