专利名称：METHOD AND APPARATUS FOR ACHIEVING
LOW POWER CONSUMPTION DURINGPOWER DOWN
发明人：Duc V. Ho,Scott E. Smith申请号：US10797240申请日：20040310
公开号：US20050201178A1公开日：20050915
专利附图：
摘要：The present technique relates to a method and apparatus to provide a deeppower down mode. In a memory device, such as DRAM or SRAM, various internal voltage
buses provide power throughout the semiconductor chip. In a deep power down mode,grounding devices may be utilized to ground the internal voltage buses. With the internalvoltage buses grounded, the outputs of the level shifters, which are control signals, mayneed to be forced into specific states. Through the use of the grounding devices andlevel shifters, leakage may be reduced and latch-up conditions may be reduced. As aresult, the operation of the semiconductor chip may be enhanced because the problemsassociated with grounding the internal voltage buses may be diminished.
申请人：Duc V. Ho,Scott E. Smith
地址：Allen TX US,Plano TX US
国籍：US,US
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